The present invention relates to semiconductor devices and, in particular, to semiconductor memory devices that may experience read failures and to related methods of analyzing such read failures.
Semiconductor memory devices are generally classified into volatile memory devices, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), and nonvolatile memory devices such as electrically erasable and programmable read-only memories (EEPROMs), ferroelectric RAMs, phase-changeable RAMs, magnetic RAMs (MRAMs), and flash memories. Volatile memories lose the data stored therein if the power supply to the memory is interrupted. In contrast, nonvolatile memories retain the data stored therein even when power to the memory is shut off. Flash memories are used as storage media in a wide variety of applications due to, for example, their relatively fast programming speeds, low power consumption and large data capacity.
A flash memory includes a memory cell array for storing data. The memory cell array will typically include a plurality of memory blocks. Each memory block, in turn, includes a plurality of pages, and each page is formed from a plurality of memory cells. Typically, a flash memory will perform an erase operation on an entire memory block, while read and write operations are performed on one page at a time.
In a flash memory that uses two-level memory cells, each memory cell may be classified as an “on-cell” or as an “off-cell” based on the threshold voltage distribution of the cell. An on-cell stores data “1,” which is referred to as an “erased cell.” An off-cell stores data “0,” which is referred to as a “programmed cell.” Each on-cell may be conditioned, for example, to have a threshold voltage between −3 V and −1 V, while each off-cell may be conditioned, for example, to have a threshold voltage between +1 V and +3 V.
A flash memory includes a plurality of cell strings. A cell string is formed of a string selection transistor that is coupled to a string selection line, a plurality of memory cells that are each coupled to respective ones of a plurality of word lines, and a ground selection transistor that is coupled to a ground selection line. A source/drain region of the string selection transistor is connected to a bit line and a source/drain region of the ground selection transistor is connected to a common source line.
During a read operation, a selective read voltage (Vrd) of about 0 V is applied to a selected word line while a de-selective read voltage (Vread) of about 4.5 V is applied to each de-selected word line. The de-selective read voltage has a level that is sufficient to turn on the memory cells that are coupled to the de-selected word lines.
A read failure may occur for a variety of reasons during a read operation. Herein, a “read failure” refers to a read operation in which (1) a memory cell that has been programmed as an on-cell (data value of “1”) is sensed as an off-cell (data value of “0”) or (2) a memory cell that has been programmed as an off-cell (data value “0”) is sensed as an on-cell (data value “1”).
A read failure may occur because of (1) charge leakage, (2) soft-programming and (3) over-programming. A read failure due to charge leakage may occur when charges are released from a programmed cell into a channel. A read failure due to soft-programming may occur when a threshold voltage of an on-cell is increased. A read fail due to over-programming may occur when a threshold voltage of an off-cell is increased.